1. Field of the Invention:
This invention relates to semiconductor memory sense circuits particularly to variable threshold transistor memory sense circuits.
2. Description of the Prior Art
A semiconductor memory includes a plurality of memory cells which are normally arranged in an array having rows and columns. A memory cell may contain one or two variable threshold transistors such as a metal nitride oxide semiconductor (MNOS) transistor. Information is written into and read out of the memory array by selecting the row and column pertaining to the desired memory cell with a row decoder and column decoder. To write information into a single transistor memory cell, voltages are placed across the variable threshold transistor to shift the threshold voltage of the transistor to a new threshold voltage such as from -2 volts to -8 volts. To write information into a memory cell containing two transistors, voltages are placed across each variable threshold transistor to shift the threshold voltage of each transistor to different threshold voltages such as -2 volts and -8 volts for one information state and -8 volts and -2 volts for the other. The threshold voltage of the transistor or pair of transistors is read out by placing a predetermined voltage on the selected row of the memory cell which is coupled to the gates of the variable threshold transistors in the row. The voltage is normally selected to cause the variable threshold transistor to turn on or source follow if its threshold voltage is -2 volts and to remain off or to conduct a very small amount of current, in the range of microamperes, if the threshold voltage is at -8 volts. In the prior art, the current passing through the variable threshold transistor between the source and drain electrodes is detected or sensed by comparing it with the current passing through a reference load or through another variable threshold transistor which has a predetermined threshold voltage. The sense circuit normally used to compare the conductivities of two load elements is a cross-coupled latch which is initially set so that neither transistor in the latch conducts current. For example, a cross-coupled latch consisting of two P-channel enhancement mode, field effect transistors initially has its source, drain and gate electrodes charged to the same voltage. At the appropriate time for sensing, the gate of the first transistor and the drain of the second transistor are coupled to one load element of the gate of the second transistor and the drain of the first are coupled to a second load element. As the two load elements conduct current, the gates of the two transistors drop in voltage from their percharge potential. The load element having the greatest conductivity will pull the gate, for example, of the first transistor to a lower potential first resulting in turning on the first transistor. The first transistor supplies current to its drain and the other load element tending to pull the voltage at the other load element and the gate of the second transistor positive, tending to turn the second transistor off. The gate of the first transistor continues to drop in potential while the gate of the second transistor is charged up, causing the cross-coupled pair of field effect transistors to latch into a stable state.
For lower power, the detection latch may comprise a cross-coupled pair of complementary metal oxide semiconductor (CMOS) NOR gates.
When the detection latch is in the stable state, one of the load elements has been charged positive to the positive supply voltage. If the other side of the load element is coupled to the negative voltage supply, then a DC path from the positive to the negative voltage supply may exist if the load element conducts current. Even though the current conducted by the load element may be small, in the range of microamperes, considerable power may be dissipated because of the voltage across the load element such as 30 volts.
With the detection latch in the stable state and with one side of the latch charged to a positive voltage such as +10 volts, read enhancement may occur during reading when the gate of the variable threshold transistor (acting as a load element) is negative. Read enhancement is variable threshold transistors occurs when the voltage during reading across the gate and source electrodes is sufficient to shift the threshold voltage, V.sub.T, more negative. In fast (1 microsecond write pulses) random access memory (RAM) applications, repeated read cycles could shift the threshold voltage enough so that a subsequent write cycle could not reverse the threshold voltage.
A prior art detection latch comprised of all P-channel transistors is an impedance ratio type circuit in which the voltage divided between the load element and the impedance of the latch transistors is important to assure proper voltages at a time prior to latching. This places constraints on the relative sizes of the transistors in the latch as well as the transistors in the memory array.
It is therefore desirable to provide a sense circuit which will not place a positive voltage on the source of the variable threshold transistor being read which results in read enhancement.
It is further desirable to provide an improved sense circuit which will have low power dissipation.
It is further desirable to provide a sense circuit which is not an impedance ratio type circuit where the voltage is divided between the load element and the transistors of the side of the latch circuit it is coupled to which in turn removes the constraints on the relative sizes of the transistors in the latch and the transistors used in the memory cells.